In a manufacturing process of a semiconductor device, a pattern formed on a mask is transferred to a wafer (semiconductor substrate) using a reduction projection exposure apparatus. Specifically, an exposure apparatus called a stepper or a scanner decreases a circuit pattern provided on the mask in size from about one-fourth to one-fifth and projects the pattern onto the wafer.
Recently, along with high accumulation and high capacity of Large-scale integrated circuits (LSI), the width of circuit lines required for semiconductor devices is ever narrowing. Along with this tendency, the width of the lines of a pattern formed on a mask is getting narrower. For example, in recent typical logic devices, it is required to form a pattern having a line width of several ten nanometers.
Manufacturing the LSIs incurs large costs. For this reason, it is important to increase a yield rate in a manufacturing process. Examples of major factors that decrease a fabrication yield of LSIs include a defect of a pattern formed on a mask, and a fluctuation of processing conditions in a manufacturing process of a semiconductor device. To eliminate the factors, the defect of the mask is detected through an inspection, or a margin is provided for the fluctuation of the processing conditions.
A method of ensuring the margin for the fluctuation of the processing conditions includes an improvement in dimensional accuracy of the pattern of the mask. As described above, miniaturization of the pattern of the mask is ongoing. For the reasons described above, in the inspection of the mask, it is required to detect a difference in shape and dimensions of a fine pattern as a defect. Specifically, it is required to detect a shape defect, such as a short-circuit defect in which lines are short-circuited and an open defect in which a line is disconnected, and a defect caused by an inappropriate gap between adjacent patterns due to line-width abnormality of the pattern or a positional deviation of the pattern.
As one of methods of forming a fine circuit pattern, there is the Optional Proximity Correction (OPC) technique. The OPC technique is used to preliminarily correct a pattern to be formed on a mask so that a pattern to be formed on a wafer matches with the design pattern.
In the OPC technique, an assist pattern is arranged on the side of a main pattern. With this, light energy of light incident on an area of the main pattern is ensured, and the formability of the main pattern on the wafer is improved. The assist pattern is not transferred to the wafer, and thus even if a defect is detected in the assist pattern in the inspection of the mask, the defect does not result in a practical problem. Therefore, such a defect should be distinguished as a fault defect from a true defect.
However, in masks of recent times in which the miniaturization advances, it becomes difficult to distinguish between the true defect and the fault defect. That is, it is difficult to determine whether a detected defect is a defect that should be detected as a true defect simply by comparing reference image data generated based on the design data with optical image data of the pattern acquired by the inspection apparatus.
It is proposed to incorporate simulation into the method of determining a defect.
For example, Japanese Patent Application KOKAI Publication No. 2012-252055 describe an inspection method in which simulation of the optical system of the inspection apparatus is performed to obtain information on the shape of the pattern of the mask which is to be detected when the mask is inspected by the inspection apparatus. It is determined whether or not a result of the inspection is within an acceptable range, using the information.
Japanese Patent Application KOKAI Publication No. 2009-105430 discloses a method of simulating a lithographic design including a number of polygons arranged in a predetermined region. Specifically, in Japanese Patent Application KOKAI Publication No. 2009-105430, FIG. 4 illustrates that a spacial image is generated using a bit map image on a basis of polygon design data (Box 126), and resist-modeling or simulation is executed by using the spacial image (Box 128). Further, FIG. 7 of Japanese Patent Application KOKAI Publication No. 2009-105430 disclose a technique of estimating, by simulation, the spacial image of the wafer based on the optical image obtained by the mask inspection apparatus. These techniques may identify correctness and defectiveness in the spacial image of the wafer or in the feature of the wafer obtained as a result of the wafer generation process, such as a reaction of a photoresist by means of exposure light.
Japanese PCT National Publication No. 2001-516898 describes 1) in the mask inspection system, it is important to determine whether or not a defect under a specific condition in the lithographic process is transferred to a photoresist in the lower layer; 2) if the defect of the mask is not printed or does not influence the lithography process, acceptable lithography can be achieved even by use of the mask including the defect. Japanese PCT National Publication No. 2001-516898 further discloses the inspection apparatus that receives a defective area image including a part of the mask image to generate a simulated image. This simulated image includes a simulation of an image transferred to the wafer.
However, the simulation requires various parameters, and has difficulties in which setting of a threshold to distinguish between a true defect and a fault defect becomes ambiguous. Further, there is also a difficulty that a difference between the simulation result and the actual inspection result occurs depending on the type of a pattern to be formed on the mask or the quality of the mask.